Information processing apparatus have been finding wider use and have been required to have an ability to perform sophisticated arithmetic processing and to process a large amount of data such as of images and moving pictures at a high speed. There has heretofore been known an arrangement including, in addition to a host processor, a DSP (Digital Signal Processor) or an ASIC (Application Specific Integrated Circuit) dedicated to certain arithmetic operations and processing operations for reducing the processing burden on the host processor, namely a CPU or the like, to increase the processing capability of an information processing apparatus.
In recent years, information processing apparatus have been required to perform compressing/expanding processes and arithmetic processing operations according to various standards on multimedia data such as of images, moving pictures, speech, music, etc., and various protocols have been used for communication processes for sending and receiving various data via networks such as the Internet, etc. Furthermore, concern over the security of information sent and received over networks has resulted in needs for encrypting processes for information security and decrypting processes for decrypting encrypted information. If the information processing apparatus incorporate many DSPs and ASICs for performing such processes, then the information processing apparatus will be large in circuit scale and cost.
There has been known an arrangement wherein an information processing apparatus incorporates a data processing device comprising a reconfigurable device such as an FPGA (Field Programmable Gate Array), a CPLD (Complex Programmable Logic Device), or a DRP (Dynamically Reconfigurable Processor), and, when necessary, the program in the data processing device is rewritten to process data for thereby increasing the throughput of the information processing apparatus, reducing the cost thereof, and meeting various processing demands.
The reconfigurable device includes an internal memory for storing programs (object codes) therein. Under the control of a CPU, object codes stored in an external memory are loaded into the internal memory, and a circuit is configured in the reconfigurable device according to the loaded object codes for processing data input to the circuit.
Details of the DRP are disclosed, for example, in Patent document 1 (Japanese Patent Laid-Open No. 2000-138579), Patent document 2 (Japanese Patent Laid-Open No. 2000-224025), Patent document 3 (Japanese Patent Laid-Open No. 2000-232354), Patent document 4 (Japanese Patent Laid-Open No. 2000-232162), Patent document 5 (Japanese Patent Laid-Open No. 2003-076668), Patent document 6 (Japanese Patent Laid-Open No. 2003-099409), Non-patent document 1 (Hideharu Amano, Akiya Jouraku, Kenichiro Anjo, “A Dynamically Adaptive Hardware on Dynamically Reconfigurable Processor”, IEICE Transactions, Vol. E86-B, No. 12, pp. 3385-3391, 2003). The DRP comprises an arithmetic device for performing arithmetic operations and a controller for controlling the operation of the arithmetic device. The arithmetic device comprises a plurality of small-scale arithmetic units and an interconnection device for changing connections between the arithmetic units.
The DRP is capable of performing various types of processing operations. For example, while the DRP is performing a processing operation, it may read other data from a memory and continue the processing operation using the read data. Though the DRP has an internal memory, the internal memory often has a limited storage capacity. Therefore, when the DRP needs to refer to a table or data which requires a large storage capacity while the DRP is performing a processing operation, it is necessary to access a memory which stores the table or the data. A processing method for such memory access is disclosed, for example, in Patent document 7 (Japanese Patent Laid-Open No. 2005-222141) and Patent document 8 (Japanese Patent Laid-Open No. 2005-222142).
For performing a processing operation based on an object code made up of one or more configurational information generated depending on data to be processed, the data processing device of the background art employs a method of performing the processing operation by directly designating the position of the configurational information that is stored in the data processing device.
The configurational information refers to information required to hypothetically configure a circuit in the data processing device, including arithmetic instructions for arithmetic units at a certain time, information representative of the connected relationship between the arithmetic units in the interconnection device, and information representative of the relationship between an event signal and configuration information to be selected next depending on the event signal. The object code indicates a set of configurational information required to perform a desired processing operation.
According to the above method, however, when a plurality of object codes are installed in the data processing device, if the stored positions of the configurational information of the object codes overlap each other, then the object codes need to be combined again so that they will not overlap each other.
If a plurality of object codes or a large-sized object code is installed in the data processing device beyond the number of items of configurational information that can be held by the data processing device, then the data processing device needs to perform a series of processing operations including shutdown, replacement of the object code or codes that have been held, and restart. In order to perform such operations, the data processing device requires an external processing unit such as an MPU or the like. Since the data processing device of the background art can have configurational information installed only in the location determined at the time the object codes are combined, if configurational information made up of codes having the same function is to be installed in a different location, then it is necessary to prepare a plurality of items of configurational information made up of is codes having the same function. As the configurational information cannot be shared, the data processing device has been problematic in that its processing operations tend to be slow because the data processing device holds a plurality of items of identical configurational information and rewrites the same configurational information.